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sy88349ndl 2.5gbps burst-mode limiting amplifier with ultra-fast signal assert timing january 2012 2 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 general description the sy88349ndl is a high-sensitivity, burst-mode capable limiting post amplifier designed for optical line terminal (olt) receiver applications. the sy88349ndl satisfies the strict timing restrictions of the gpon standards by providing ultra-fast loss-of-signal (los) or signal-detect (sd) output. auto reset and manual reset options are provided to control los/sd output timing. for increased flexibility, this devic e also includes an option to select between los or sd output. the device can be connected to burst-mode capable transimpedance amplifiers (tias) using ac or dc coupling. the sy88349ndl generates a high-gain los or sd lvttl output. a programmable los/sd level set pin (los/sd lvl ) sets the sensitivity of the input amplitude detection. when los/sd sel pin is left open or tied to v cc , jam is active high, sd is selected and asserts high if the input amplitude rises above the threshold sets by los/sd lvl and de-asserts low otherwise. when los/sd sel pin is set low or tied to gnd, jam is active low, los is selected and asserts low if the input amplitude rises above the threshold sets by los/sd lvl and de-asserts high otherwise. the los/sd output can be fed back to the jam input to maintain output stability under an invalid signal conditions. typically, 4db ? 5db sd hysteresis is provided to prevent chattering. the sy88349ndl also features a selectable proprietary noise discriminator that aids by filtering out input signals that do not qualify as a 2.5gbps gpon preamble signal in the initial startup phase. this feature minimizes false sd asserts that can be triggered by random noise. the sy88349ndl operates from a single +3.3v power supply, over temperatures ranging from ?40 ? c to +85 ? c. with its wide bandwidth and high gain, signals up to 2.5gbps and as small as 5mvpp can be amplified to drive devices with cml inputs. data sheets and support documentation can be found on micrel?s web site at www.micrel.com . features ? <5ns sd assert (los deassert) time ? proprietary noise discriminator feature ? option to auto reset or manual reset los/sd output ? selectable los/sd option ? up to 2.5gbps operation ? low-noise cml data outputs ? 5mvpp input sensitivity ? high-sensitivity los/sd detect ? lvttl los/sd output with an external pull-up resistor ? squelching function to disable output ? programmable los/sd level set (los/sd lvl ) ? single 3.3v power supply ? available in a 16-pin (3mm ? 3mm) qfn package applications ? xgpon.1/gepon/gpon ? gigabit ethernet ? fibre channel ? oc-3/12/24/48 sonet/sdh ? high-gain line driver and line receiver ? low-gain tia interface markets ? ftth ? datacom/telecom ? optical transceiver
micrel, inc. sy88349ndl january 2012 3 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 ordering information part number package type operating range package marking sy88349ndlmg lead-free 16-pin 3mm ? 3mm qfn ?40 ? c to +85 ? c 349n with pb-free bar-line indicator SY88349NDLMGTR (1) lead-free 16-pin 3mm ? 3mm qfn ?40 ? c to +85 ? c 349n with pb-free bar-line indicator note: 1. tape & reel. pin configuration 16-pin 3mm ? 3mm qfn (qfn-16) pin description pin number pin name pin function 1, 4 din, /din data inputs. if ac -coupled, terminate each pin to v ref with 50 ? . 2 vref reference voltage output. typically v cc ? 1.3v. 3, 11, 8 gnd device ground. 10 /auto reset lvttl input. this pin is internally connected to a 25k ? pull-up resistor and defaults to high. when this pin is low or tied to ground, the /auto reset function is enabled and sd de- asserts or los asserts within 100ns (typical) afte r the last high-to -low transition of the burst input. when this pin is left floating or not connec ted, the auto reset function is disabled and the sd de-assert or los assert must be fo rced by using the manual reset function. 5, 16 vcc positive power supply.
micrel, inc. sy88349ndl january 2012 4 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 pin description (continued) pin number pin name pin function 6 reset lvttl input. apply a high-level signal ( ? 2v) to this pin to discharge the time constant and reset the signal de-assert time or los assert time within 5n s. reset defaults to low if left floating. if the /auto reset function is not used, this reset function needs to be used to quickly de- assert the sd or assert los. this pin is internally connected to a 25k ? pull-down resistor and defaults to low. 7 sd/los lvttl output. signal-detect (sd) asserts high when the data input amplitude rises above the threshold sets by sd lvl . conversely, loss-of-signal (los) de-asserts low when the data input amplitude rises above the threshold set by los lvl . 12, 9 dout, /dout cml outputs. when jam disables the device, output dout is forced to logic low and output /dout is forced to logic high. 13 los/sd sel allows the user to select between whether lo s or sd is outputted on the los/sd pin and whether the noise discriminator is enabled or disabled. please see truth table for more information. also controls the polarity of t he jam input. when sd (regardless of the noise discriminator status) is selected, jam is active high and los/sd (pin 7) operates as signal detect. conversely, when los is selected, ja m is active low and los/sd operates as loss- of-signal. pin must be tied to one of the four options and cannot be left open. 14 los/sdlvl voltage input. sets the loss of signal/signal de tect level. a resistor from this pin to v cc sets the threshold for the data input amplitu de at which los/sd will be asserted. 15 jam lvttl input. this jam input acts as a squelch function and switches its polarity depending on los/sdsel status. when los is selected, this pin is active low. when sd is selected, this pin is active high. to create a squelch functi on, connect jam to los/sd. when jam disables the device, output q is forced to logic low and out put /q is forced to logic high note that this input is internally connected to a 25k ? pull-up resistor. truth table for sd/los select and noise discriminator function los/sdsel pin los/sd selection noise discriminator input to jam outputs 0 ? to vcc sd enabled high enabled 0 ? to vcc sd enabled low disabled 16k ? to vcc sd disabled high enabled 16k ? to vcc sd disabled low disabled 16k ? to gnd los disabled high disabled 16k ? to gnd los disabled low enabled 0 ? to gnd los enabled high disabled 0 ? to gnd los enabled low enabled
micrel, inc. sy88349ndl january 2012 5 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) supply voltage (v cc )................................... -0.3v to +4.0v input voltage (din , /din) .......................................0 to v cc output current (i out ) continuou s........................................................ 50ma surge .............................................................. 100ma en voltage ...................................................... -0.3v to v cc v ref current ......................................... ? 800 a to +500 a sd lvl voltage ....................................................v ref to v cc lead temperature (solde ring, 20sec .)..................... 260c storage temperature (t s ) ....................... ?65c to +150c operating ratings (2) supply voltage (v cc ).................................... +3.0v to +3.6v ambient temperature (t a ) ..........................?40c to +85c junction temperature (t j ) ........................?40c to +125c junction thermal resistance (3) qfn ( ? ja ) still-air ................................................60c/w qfn ( ? jb ) junction-to- board ..............................38c/w dc electrical characteristics v cc = 3.0 to 3.6v; t a = ?40 ? c to +85 ? c, typical values at v cc = 3.3v, t a = 25 ? c. symbol parameter condition min. typ. max. units i cc power supply current no output load 90 120 ma los/sd lvl los/sd lvl voltage v ref v cc v v oh cml output high voltage note12 v cc ? 0.020 v cc ? 0.005 v cc v v ol cml output low voltage note 12 v cc ? 0.475 v cc ? 0.4 v cc ? 0.350 v v offset input offset voltage 1 mv v ihcmr(diff) common-mode range (differential) note 4 gnd +1.4 vcc v v ihcmr(se) common-mode range (single ended ) note 4 gnd +1.2 v cc v v ref reference voltage v cc ? 1.48 v cc ? 1.32 v cc ? 1.16 v i din input sink current (din and /din) vin =vih 8.5 20 a lvttl dc electrical characteristics v cc = 3.0 to 3.6v; t a = ?40 ? c to +85 ? c, typical values at v cc = 3.3v, t a = 25 ? c. symbol parameter condition min. typ. max. units v ih lvttl input high voltage 2.0 v v il lvttl input low voltage 0.8 v i ih_jam jam input high current v in = v cc v in = 2.7v 20 20 a i il_jam jam input low current v in = 0.5v ? 0.3 ma i ih_ar /autoreset input high current v in = v cc v in = 2.7v 100 20 a i il_ar /autoreset input low current v in = 0.5v ? 0.3 ma i ih_reset reset input high current v in = v cc v in = 2.7v 300 250 a i il_reset reset input low current v in = 0.5v 0 ma v oh sd/los output high level i oh = ? 100ua 2.1 2.7 v v ol sd/los output low level i ol = 100ua 0.35 0.5 v
micrel, inc. sy88349ndl january 2012 6 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 ac electrical characteristics v cc = 3.0v to 3.6v; r l = 50 ? to v cc ; t a = ?40 ? c to +85 ? c. symbol parameter condition min. typ. max. units t r , t f output rise/fall time (20% to 80%) note 4 150 ps t jam jam enable/disable time 2 ns t autoreset sd de-assert or los assert with auto reset enabled 75 120 150 ns t reset reset disable time note 5 5 ns t on sd assert time/los de-assert time noise discriminator bypassed 5 ns t on_nd sd assert time/los de-assert time noise discriminator enabled 7 ns deterministic note 6 15 ps pp t jitter random note 7 5 ps rms v id differential input voltage swing figure 1 5 1800 mv pp v od differential output voltage swing v id ? 18mv pp note 12 660 800 940 mv pp sd al /los dl low sd assert/los de-assert level r los/sdlvl = 10k ? (8, 10, 13) 9 mv pp sd dl/ /los al low sd de-assert/los assert level r los/sdlvl = 10k ? (10, 13) 4.5 mv pp hys l low sd/los hysteresis r los/sdlvl = 10k ? (11, 13) 6 db sd am /los dm medium sd assert/los de-assert level r los/sdlvl = 5k ? (10, 13) 9.4 12.5 15.6 mv pp sd dm /los am medium sd de-assert/los assert level r los/sdlvl = 5k ? (10, 13) 5 7 8.6 mv pp hys m medium sd/los hysteresis r los/sdlvl = 5k ? (11, 13) 3.5 5 7 db sd ah /los dh high sd assert/los de-assert level r los/sdlvl = 100 ? (10, 13) 27 35 45 mv pp sd dh /los ah high sd de-assert/ los assert level r los/sdlvl = 100 ? (10, 13) 15 21 28 mv pp hys h high sd/los hysteresis r los/sdlvl = 100 ? (11, 13) 2 4.5 6 db a v(diff) differential voltage gain 42 db s 21 single-ended small-signal gain 36 db notes: 1. permanent device damage may occur if absolute maximum ratings are exceeded. this is a stress rating only and functional oper ation is not implied at conditions other than those detailed in the operational sections of this data shee t. exposure to absolute maximum rating con ditions for extended periods may affect device reliability. 2. the data sheet limits are not guaranteed if t he device is operated beyond the operating ratings. 3. thermal performance assumes the use of a 4-layer pcb. ex posed pad must be soldered to the device?s most negative potential o n the pcb . 4. vihcmr is defined as common mode range of the vih level on din and /din. it is the most positive level of the differential i nput signal when driven differentially or is the reference leve l on din\ when being driven single ended. 5. amplifier in limiting mode. input is a 200mhz square wave. 6. deterministic jitter measured using 2.5gbps k28.5 pattern, v id = 10mv pp . 7. random jitter measured using 2.5gbps k28.7 pattern, v id = 10mv pp . 8. sd is the opposite polarity of los. therefore, an sd assert parameter is equivalent to a los de-assert parameter and vice ve rsa. 9. see ?typical operating characteristi cs? for graphs showing input signal vs. sd assert/los de-assert time at various r los/sdlvl settings. 10. see ?typical operating characteristics? for graph showing how to choose a particular r los/sdlvl for a particular assert and its associated de-assert amplitude. 11. this specification defines el ectrical hysteresis as 20log(sd assert/sd de-a ssert). the ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2 depending upon the level of received optical power and rosa characteristics. based upon that ra tio, the optical hysteresis corresponding to the electrical hysteresis range 2db-5db, shown in the ac characteristics table, will be 1db-4db opt ical hysteresis. 12. v ol and v oh are measured with outputs loaded with 50 ohms as shown in figure 3b and v od is measured in accordance with figures 3a and/or 3b. 13. all sd assert (los de-assert) level, sd de-assert (los assert) level and hysteresis s pecifications listed above are spec ified using a 1010 pon preamble data pattern at the specified data rate of 2.488 gbps.
micrel, inc. sy88349ndl january 2012 7 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 typical operating characteristics v cc = 3.3v, t a = 25 ? c, r l = 50 ? to v cc , unless noted. los assert/de-assert levels 1 10 100 0.01 0.1 1 10 los/sdlvl resistor (kohm) signal amplitude (mv) los/sd hysteresis 2 3 4 5 6 7 8 0.01 0.1 1 10 los/sdlvl resistor (kohm) hysteresis (db) note: sd/los sensitivity with rlos/sd at 0 ? is the same as with 0.01 k ? input signal and los de-assert with noise discriminator bypass and without jam input signal and los with noise discriminator engaged and without jam
micrel, inc. sy88349ndl january 2012 8 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 functional diagram
micrel, inc. sy88349ndl january 2012 9 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 detailed description the sy88349ndl is a high-sensitivity limiting post amplifier which operates on a +3.3v power supply over the industrial temperature r ange. signals with data rates up to 2.5gbps and as small as 5mvpp can be amplified. depending on the los/sdsel option, the sy88349ndl can generate an sd or los output, and allow feedback to the jam input for output stability. los/sd lvl sets the sensitivity of the input amplitude detection. to satisfy the stringent timi ng requirements of the gpon specifications, the signal detect circuit offers 5ns sd assert (los de-assert) time and the option to de-assert sd (assert los) using th e /auto reset or manual reset function. when /auto reset is enabled, sd de-asserts/los asserts automatically within approximately 120ns after the last high-to-low transition of the input burst. when t he /autoreset function is disabled, the sd de-assert/los assert time can be reset by using the provided reset pin. input buffer figure 2 shows a simplified schematic of the input stage. the high sensitivity of the input amplifier allows signals as small as 5mvpp to be detected and amplified. the input buffer can allow input signals as large as 1800mvpp. input signals are lin early amplified with a typically 48db differential voltage gain until the outputs reach 1500mv pp (typical). applicat ions requiring the sy88349ndl to operate with high-gain should have the upstream tia placed as close as possible to the sy88349ndl?s input pins. this ensures the best performance of the device. output buffer the sy88349ndl?s cml output buffer is designed to drive 50 ? lines. the output buffer requires appropriate termination for proper operation. an external 50 ? resistor to v cc for each output pin provides this. figure 3 shows a simplified schematic of the output stage. loss of signal/signal detect the sy88349ndl generates a chatter-free signal-detect (sd) or los lvttl output, as shown in figure 4. a highly-sensitive signal detect circuit is used to determine that the input amplitude is too small to be considered a valid input. los asserts high if the input amplitude falls below the threshold sets by los/sdlvl and de-asserts low otherwise. sd asserts high if the input amplitude rises above threshold set by los/sdlvl and de-asserts low otherwise. los/sd can be fed back to the jam input to maintain output stability under the absence of an invalid signal condition. typically, a 4.5db to 5.5db hysteresis is provided to prevent chattering. los/sd level set a programmable los/sd level pin (los/sd lvl ) sets the threshold of the input am plitude detection. connecting an external resistor between v cc and los/sd lvl sets the voltage at los/sd lvl . this voltage ranges from v cc to v ref . the external resistor creates a voltage divider between v cc and v ref , as shown in figure 5. set the los/sd lvl voltage closer to v ref or more sensitive los/sd detection or closer to v cc for higher inputs. note that the sy88349ndl is designed for use in the burst mode pon application where every burst is preceded with several bytes of a 1010 pon preamble pattern. therefore the sd assert (los de-assert) is designed to trigger on the first few bits of this preamble pattern and therefore the sd/los thresholds outlined in the ac electrical characterist ics are specified using this preamble pattern. once the sd is asserted (los de- asserted), the sd is de-asserted (los asserted) only by the application of a manual reset or an auto reset if the auto reset is activated, the auto reset asserts a reset approximately 120 ns after the last negative going transition of t he data as explained earlier. noise discriminator the noise discriminator feature is intended for the high- gain burst-mode tias where noise can trigger a false los deassert or sd assert while no input data is present. the noise discriminator will filter input data through a series of specializ ed circuitry that will only trigger los/sd on the rising edge of a valid pon 2.488 gbps preamble bit stream (10101). the sy88349ndl noise discriminator is designed to accept a 2.488 gbps +/-300 mbps preamble burst. any other bit pattern will be rejected. if this part is used at any other data rate, the noise discriminator should be disengaged. the noise discriminator, implemented in the edge detector circuit, can be selected or bypassed by selecting the proper resistor value using the settings at los/sdsel pin. refer to the ?truth table for sd/los select and noise discriminator function? found on page 3 for more detailed information.
micrel, inc. sy88349ndl january 2012 10 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 timing diagrams a) no manual reset and /autoreset tied high (noise discriminator off) b) no manual reset and /autoreset tied high (noise discriminator on) c) no manual reset and /autoreset tied low (noise discriminator off) d) no manual reset and /autoreset tied low (noise discriminator on) e) manual reset and /autor eset tied high or low (noise discriminator off) f) manual reset and /autoreset tied high or low (noise discriminator on)
micrel, inc. sy88349ndl january 2012 11 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 timing diagrams (continued) g) manual reset pulse and /autoreset tied low (noise discriminator off) h) manual reset pulse and /autoreset tied low (noise discriminator on)
micrel, inc. sy88349ndl january 2012 12 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 input signal amplitude figure 1. vis (single ended) and vid (differential) definition
micrel, inc. sy88349ndl january 2012 13 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 simplified circuit diagrams figure 2. simplified input structure figure 3a. simplified output structure with ac-coupled termination figure 3b. simplified output structure with dc-coupled termination figure 4. simplified los/sd output structure figure 5. simplified los/sd lvl setting circuit
micrel, inc. sy88349ndl january 2012 14 m9999-010212-c hbwhelp@micrel.com or (408) 955-1690 package information 16-pin qfn (qfn-16) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to t he accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for it s use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether expre ss, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of an y patent, copyright or other intellectual p roperty right micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significan t injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk and purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2011 micrel, incorporated.

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